Microdevices, such as integrated microcircuits and microelectromechanical systems (MEMS), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microdevices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microdevice fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.
Several steps are common to most design flows for integrated microcircuits. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). As part of the creation of a logical design, a designer will also implement a place-and-route process to determine the placement of the various portions of the circuit, along with an initial routing of interconnections between those portions. The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly provide the same behavior as the original hardware design language description of the circuit design. This analysis is sometimes referred to as “formal equivalence checking” or more generally “formal verification.”
Once the relationships between circuit devices have been established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components (e.g., contacts, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. “Place and route” tools, such as the Olympus-SoC tool, available from Mentor Graphics® Corporation of Wilsonville, Oreg., are used for this task. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines then are then placed between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices.
Typically, a designer will perform a number of analyses on the resulting layout design data. For example, with integrated circuits, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships as described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, the layout design may be modified to include the use of redundant geometric elements or the addition of corrective features to various geometric elements, to counteract limitations in the manufacturing process, etc. For example, the design flow process may include one or more resolution enhancement technique (RET) processes, that modify the layout design data to improve the usable resolution of the reticle or mask created from the design in a photolithographic manufacturing process.
After the layout design has been finalized, it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. The written masks or reticles then can be used in a photolithographic process to expose selected areas of a wafer to light or other radiation in order to produce the desired integrated microdevice structures on the wafer.
Returning to the place-and-route process, this process typically begins with a circuit design described in a register transfer language. Using a place-and-route tool, a designer will place portions of the circuit design relative to each other in a geographic design environment. While these circuit design portions correspond to segments of code in a register transfer language, they typically are represented in the geographic design environment as blocks. Once the blocks have been placed relative to each other, wiring lines are routed between the blocks. These wiring lines represent the interconnections that will be formed between the components of the electrical device. The routing typically takes place in two stages: a coarse or track routing stage, in which groups of wires are routed together between blocks, and detailed routing where the position of individual wires are adjusted.
Initially, the routed wires may not convey clock signals or data signals between the circuit devices sufficiently fast to provide operation times that will perform at the desired clock frequency. In an attempt to optimize the operational timing for the design, a routing tool will make changes to the circuit design according to a variety of routing heuristics. For example, the routing process may insert buffers into the wires, which will speed up the transmission of a signal by amplifying it. The routing tool also may make straighten some lines, or substitute alternate logic that processes signals faster. Still further, the relative position of the blocks may be further adjusted. Some place-and-route tools may employ from 20-30 different techniques to improve ensure the accurate operation of a circuit manufactured from the circuit design.
Various optimization techniques like timing optimization techniques may take place at different times over the course of the place-and-route operation. For example, these optimization techniques may be employed both before and after data signal interconnect routing, and before and after clock signal synthesis. As a result, these optimization techniques may take up to 60%-70% of the execution time of a place-and-route process. Accordingly, reducing the time required for these optimization techniques may significantly reduce the execution time of a place-and-route process.
Various conventional place-and-route tools employ parallel processing to expedite routing optimization techniques, by dividing the implementation of these techniques across multiple processors. For example, some conventional place-and-route tools can divide a hierarchically-organized circuit design into parts based upon its hierarchical structure. Different parts can then be assigned to different processors for implementation of one or more routing techniques. With modern circuit designs, however, the cells that make up a hierarchical structure can be very large, leading to an inefficiently large partition granularity. Also, there may be several clocks signals in a single cell, adding to complexity to the optimization techniques.